Reference is hereby made to UK Pat. No. 2095039 A H05 K 7/14, Date of Patent Feb. 10, 1982, and U.S. Pat. No. 4,823,233 H05K 7/20, Patent Date Apr. 18, 1989.
A circuit assembly includes a mounting structure having walls with conductor strips running along the length of the structure. Plate members carrying components such as integrated cicuits have conductive areas which contact the conductor strips when the members are inserted into the structure. The walls may include slots into which the plate members are slidably engaged. The support structure thus provides physical support for the members as well as electrical interconnection therebetween. Cooling arrangements for the assembly can include apertures in the walls and/or finning.
The disadvantages of this construction are as follows:
all electrical interconnections between the plates are by slidable contacts in the walls of the mounting structure, which considerably reduces the reliability of the assembly; PA1 complete disassembly of the construction is necessary when repair is needed, because no plate can otherwise be removed. PA1 apertures in the walls and/or finning reduce the density of packing many times and make the assembly comparable to the conventional methods of assembly.
The Patents of interest also include U.S. Pat. No. 5,373,189 HO1L 23/02, Dec. 13, 1994.
A three-demensional multichip module having a plurality of bidimensional elementary electronic modules, each incorporating at least one chip, a support on which is placed the chip and a conductive interconnection network or array covering an upper surface of the support. These elementary modules are substantially superimposed and are interconnected by means of their interconnection networks. The underside of a support has a cavity appreciably greater than that of the chips so that the carrier of the first elementary module must be above the chip located on the second elementary module. Each elementary module. Each elementary module has at least one contacting area or short bonding pad disposed on one plane of the support and connected with the chip through interconnection networks; every pad has contact with the pads of the adjacent elementary modules (upper module and bottom module) in order to provide electrical connection between elementary modules. The electronic modules are arranged essentially one above the other and displaced, being protected from one another so that the pads of each carrier did not cover the carrier of the upper electronic module, and that is why, the electrical contacting between the wires of said pads is allowed. Each electronic module has a plurality of crystals interconnected by means of interconnection networks.
This design has all limitations of a traditional stack module: heat removal from each carrier and from the module as a whole is not provided for; modules are bound to be of different hight depending on their content and particular application, hence, inefficient space utilization when module is assembled on the backplane (FIG. 3a); if a number of external leads is large, they collect on the bottom carrier thereby increasing its size, while close spacing of the external leads makes multilayer mounting on the backplane expensive and unreliable. Furthermore, the carriers are interconnected only through the pads and by soldering of wire leads with the result that the overall number of interconnections increases, with a loss in the structure reliability.
In a memory module configuration developed at company Cubic Memory, the starting component is wafer segment comprising four die of dynamic memory 16 Mbit each. This wafer segment is sliced from a semoconductor plate 8 inches in diameter, ground to 0.2-03 .mm thickness. Each wafer is covered with an insulating polyamide film in which windows are disposed through normal photo lithographic technique on die contact pads. Traces are disposed on the surface of the wafer to interconnect the die and to form external zones of conducting for each wafer. A second insulating film may be applied, windows provided and traces disposed because in memory circuits it is necessary to connect in parallel a large number of contact pads lying in the same plane. The wafers are joined by vertical volume buses which penetrate to the bottom layer forming the module's exit contacts intended for the surface-mount of the module. This configuration may use wafers not only with four die, but with three suitable die as well. CAD provides all possible arrangements for wafers with any disposition of the suitable die. The wafers are not subjected to burn-in but rather are controlled on a warmed up table.
Having all shortcomings of a conventional stack module, this design aims to obtain a "pure" memory and does not provide for a controller, decoupling capacitors and other "strapping" elements, in other words, the structure is not versatile. Furthermore, an attempt to keep the module hight as small as possible resulted in a loss of over 70% of serviceable die not included into the "threes" and "fours" of the operating wafers. The structure is expensive to manufacture (on a level of air-borne equipment), and not very reliable in operation on the account of the elimination of the burn-in step.
Dense-Pac company has attempted to circumvent the last-mentioned shortcoming for a structure comprising 2 modules of 8 minipackages each with static memory chips in each module. The modules and decoupling capacitors are mounted on the backplane with external pins. The packages are interconnected along the module edges in a bus-type mode. Since the physical volume of this package is 16 times that of the Cubic Memory structure, convective heat dissipation creates better thermal conditions. Not only "pure" memory has been attempted but all circuitry was mounted on the backplane in order to imitate a complete memoty cuircuit. However other disadvantages of a stack packaging could not be avoided, and packing density remained low due to the use of packaged components.
U.S. Pat. No. 5,016,138 H05K 7/20, May 15 1991 and U.S. Pat. No. 4,868,712 H05K 7/20, Sep. 19, 1989, disclose three-dimentional integrate circuit packages.
These inventions are for an improved package and packaging technology for chips from which circuit modules are formed which are denser and easier to manufacture than previously existing techniques allowed.
In accordance with these inventions, at least one chip is mounted on each of a plurality of substrates, commonly ceramic, each of which has electronically conducting traces for carrying electronic signals. The chips connect electrically to the traces by means such as wire bonds, flip-chip bonding ot TAB bonding. At least certain o the traces extend to edges of the substrate for the purpose of making electrical connections from the chips on the substrate to external circuitry. Other traces may extend from one edge of the substrate to another edge to allow the pass-through of an external signal. Other traces may extend between multiple chips on this single substrate which contains more than one chip. Pins which extend from the edge of the substrate are connected to the pattern of traces on each layer. A substrate may contain multiple layers of traces for the distribution of signals, power or ground voltages and currents. Two or more substrates are connected together, one on top of the other, to form a dense stack of electronic circuitry. Between each layer, a window frame spacer, commonly ceramic, surrounds and protects the chips. Thus, the layer consists of a substrate, traces, chips and external connections.
Side interconnection plates (SIP) electrically connect between layers. A SIP is a subsrtrate, commonly ceramic, on which appropriately placed conducting traces are formed. The SIP is coupled to receive and supply signals from and to the external conductors of each layer. At least one trace on a SIP can be so configured as to connect to each layer within the stack such as for a bus signal, ground or power supply.
Through the use of layer pass-throughs and SIPs, signals may be routed anywhere around or within the stack. SIPs may have multiple layers of traces. Three basic configurations are proposed for making external connection from the stack.
A first device uses an external side interconnection plate (ESIP). An ESIP ia similar to SIP except that ESIP is larger than the side of the stack to which is connects and certain traces on the ESIP extend beyond the edges of the stack and terminate in lands of sufficient size to receive a wire bond. A module subassembly consists of a stack, SIP(s) and ESIP and is mounted within a package base. Package pins for external connection to the completed device penetrate and terminate within the package base. Using standard integrated circuit wire bonding techniques, the ESIP bond pads are bonded to the package pins. A cap covers the stack, SIP and ESIP assembly to protect the stack from mechanical damage and to provide an hermetic seal.
A second configuration used for making external connections from the stack connects the stack to a base plate out of which extends an array of pins, similar to standard pin grid array (PGA) single chip package. Conductive traces are formed on a substrate, usually ceramic, forming the base. The base may contain multiple layers of traces as required by the specific application being implemented. Pins penetrate the layer and are electrically coupled to the traces. The traces extend to those edges which correspond to the edges of the stack to be coupled to SIPs. SIPs connect to the base as if the base was simply another layer in the stack.
A third configuration connects the stack to a second PGA-like base. In this configuration the connectors on the edges of each layer connect to the PGA base plate as if it were a SIP. Vias and traces connect the connectors on the edges of each layer to the pins on the bottom of the PGA package. If the connectors on the edges of the layers are pins then the PGA package package pins will only reside around the periphery of the base plate.
Due to high circuit density, certain applications may require that means be provided for cooling the stack. One such means for the ESIP-type module includes attaching a heat sink to the outside of the package base. Another means includes interspersing heat sink members at predetermined intervals within the stack. A third means includes interspersing liquid cooling layers at predetermined intervals within the stack.
The above configuration has distinct advantages over other attempts to tackle the heat dissipation problem, although not in the wholly rational way (convection, liquid cooling), with a result that there is a considerable loss in the packing density. The side interconnection plates make the stack virtually inaccessible for repair after assembling. The original embodiment has some of the disadvantages inherent in conventional stack modules, as is discussed in the analysis of U.S. Pat. No. 5,373,189 (except for the heat dissipation system); the embodiments presented in FIGS. 6 and 7 are free from any of the drawbacks of the stack-type module and fulfil the purpose well, however the size of the module considerably increases; the layers are joined togerther by soldering (FIGS. 13, 14, 15), which makes the structure virtually inaccessible for repair and greatly hampers the testing during assembly. In an attempt to reduce the hight of the stack, several chips (4-16) connected in parallel are mounted on each layer, which inevitably results in a multilayer pattern of each layer and, correspondingly, reduces the relaiability and increases manufacturing difficulties.
U.S. Pat. No. 5,434,745 H01L 21/18, Jul. 18, 1995, discloses a stacked silicon die carrier assembly and method for packaging and interconnecting silicon chips such as memory chips. The carrier is constructed from a metalized substrate onto which the chip is attached. The chip is wire bonded to the conductor pattern on the substrate. Each conductor is then routed to the edge of the substrate where it is connected to a half-circle of a metalized through-hole. A frame is attached on top of this substrate. This frame has also a pattern of half-circle metalized through holes that allign with the holes in the bottom substrate. The combination of the bottom substrate with the silicon die, and the frame on top, forms a basic stackable unit. Several such units can be stacked and attached on top of each other. The top unit can finally be covered with a ceramic lid that also has a matching half-circle metalized through hole pattern along its edge. To electrically interconnect the stacked assembly conductive epoxy can be applied in the grooves formed by the aligned half-circle plated through holes.
This structure has the same shortcomings as those pointed out for U.S. Pat. No. 5,373,189, Additionally, it is known, that construction in this patent repeats the decision, shown in two articles by Kavin Smith (Electronics, 1984, No. 21, p.p. 21,22)
All of the above-mentioned patents relate to three-dimensional modules and directly provide for significantly better technical characteristics of electronic equipment than previously existing traditional techniques allowed.
The closest analog to the present invention is U.S. Pat. No. 5,016,138 H05K 7/20, May 14, 1991.
As is evident from the above analysis, the principal goal in the development of multichip IC has been to use 3-D space so as to achieve high density integrated circuit packages and to improve other properties of electronic equipment. This poses a number of problems such as providing interconnections between the elements, heat dissipation, maintainability and simplicity of manufacture. The present invention aims, in particular, to provide solutions to these problems.